{"id":4054,"date":"2026-10-17T02:54:25","date_gmt":"2026-10-17T02:54:25","guid":{"rendered":"https:\/\/welleltron.com\/?page_id=4054"},"modified":"2026-10-18T01:02:43","modified_gmt":"2026-10-18T01:02:43","slug":"design-for-test","status":"publish","type":"page","link":"https:\/\/welleltron.com\/fr\/kb\/design-for-test\/","title":{"rendered":"DFT: Design for Test"},"content":{"rendered":"<style>.kb-table-of-content-nav.kb-table-of-content-id4054_6b7093-29 .kb-table-of-content-wrap{padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);}.kb-table-of-content-nav.kb-table-of-content-id4054_6b7093-29 .kb-table-of-contents-title-wrap{padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.kb-table-of-content-nav.kb-table-of-content-id4054_6b7093-29 .kb-table-of-contents-title{font-weight:regular;font-style:normal;}.kb-table-of-content-nav.kb-table-of-content-id4054_6b7093-29 .kb-table-of-content-wrap .kb-table-of-content-list{font-weight:regular;font-style:normal;margin-top:var(--global-kb-spacing-sm, 1.5rem);margin-right:0px;margin-bottom:0px;margin-left:0px;}<\/style>\n\n\n<h2 class=\"wp-block-heading\">1.what is dft testing<\/h2>\n\n\n<style>.wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0, .wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0[data-kb-block=\"kb-adv-heading4054_c110c6-6e_0\"]{font-style:normal;}.wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0 mark.kt-highlight, .wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0[data-kb-block=\"kb-adv-heading4054_c110c6-6e_0\"] mark.kt-highlight{font-style:normal;color:#f76a0c;-webkit-box-decoration-break:clone;box-decoration-break:clone;padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0 img.kb-inline-image, .wp-block-kadence-advancedheading.kt-adv-heading4054_c110c6-6e_0[data-kb-block=\"kb-adv-heading4054_c110c6-6e_0\"] img.kb-inline-image{width:150px;vertical-align:baseline;}<\/style>\n<p class=\"kt-adv-heading4054_c110c6-6e_0 wp-block-kadence-advancedheading\" data-kb-block=\"kb-adv-heading4054_c110c6-6e_0\">DFT (Design for Test or Design for Testing) is a proactive engineering methodology that integrates test-friendly features directly into the hardware architecture of a PCB during the initial schematic and layout phases.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">2. Design for Testability Objectives<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Implementing a structured dft design for test framework serves several critical economic and technical objectives:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Maximizing Fault Coverage:<\/strong> Ensuring that open circuits, short circuits, trace impedance anomalies, and sub-surface plating defects are detected instantly.<\/li>\n\n\n\n<li><strong>Minimizing Test Escapes:<\/strong> Preventing defective circuit boards from passing downstream into automated SMT assembly lines or end-user deployment.<\/li>\n\n\n\n<li><strong>Lowering Inspection Costs:<\/strong> Reducing reliance on slow, destructive physical cross-sectioning by enabling rapid, non-destructive testing (NDT).<\/li>\n\n\n\n<li><strong>Accelerating Production Throughput:<\/strong> Streamlining test execution times to support high-volume industrial manufacturing schedules.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">3. Differences DFT vs. DFM<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Many engineers confuse DFT and DFM, but they target separate stages and goals in PCB development:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><td><strong>Feature<\/strong><\/td><td><strong>DFM (Design for Manufacturing)<\/strong><\/td><td><strong>DFT  (dft test)<\/strong><\/td><\/tr><\/thead><tbody><tr><td><strong>Primary Focus<\/strong><\/td><td>Optimizing the board for physical fabrication (etching, drilling, plating, and laminate stacking).<\/td><td>Optimizing the board for electrical, mechanical, and metrological inspection.<\/td><\/tr><tr><td><strong>Key Parameters<\/strong><\/td><td>Trace\/space clearances, drill-to-copper ratios, aspect ratios, and surface finishes.<\/td><td>Test pad placement, probe access geometry, test point spacing, and boundary scan integration.<\/td><\/tr><tr><td><strong>Hardware Interaction<\/strong><\/td><td>Relies on manufacturing tools like CNC drills, milling routers, and wet processing lines.<\/td><td>Relies on diagnostic tools like ATG flying probes, ICT fixtures, and Hitachi eddy current meters.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">4. DFT Guidelines<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">To ensure seamless physical inspection, layout engineers must adhere to rigorous dft meaning layout guidelines:<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">1. Test Point Placement and Geometric Guidelines<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The physical arrangement of test points dictates whether automated equipment can access nodes quickly and without mechanical damage.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Minimum Test Pad Diameter:<\/strong> Design dedicated test pads with a minimum diameter of \u22650.8 mm(approx.31.5mils$) to ensure reliable physical contact for spring-loaded pins and flying probes.<\/li>\n\n\n\n<li><strong>Test Point Spacing (Pitch):<\/strong> Maintain a minimum center-to-center spacing of 1.27 mm to 2.54mm between adjacent test pads to prevent short circuits and probe bridging during high-density tests.<\/li>\n\n\n\n<li><strong>Symmetrical Distribution:<\/strong> Distribute test points evenly across the board surface to balance mechanical pressure when using bed-of-nails fixtures or navigating with <strong>ATG flying probe systems<\/strong>.<\/li>\n\n\n\n<li><strong>Board Edge Clearance:<\/strong> Keep all test pads at least 2.0 mm away from the physical board edge or V-CUT score lines to avoid mechanical clamping interference.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">2. Component Clearance and Keep-Out Zones<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Probes cannot inspect nodes that are physically obstructed by tall components or crowded sub-assemblies.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Height-to-Clearance Ratio:<\/strong> Ensure that the distance between a test point and a nearby component is at least equal to the component&#8217;s height (typically a <strong>1:1 clearance ratio<\/strong>), preventing probe tip skidding and mechanical collision.<\/li>\n\n\n\n<li><strong>Connector and Shielding Boundaries:<\/strong> Avoid placing test points beneath unremovable metal shields, connectors, or large electrolytic capacitors unless internal boundary-scan (JTAG) chains are implemented.<\/li>\n\n\n\n<li><strong>SMT Proximity Control:<\/strong> Keep test pads away from delicate surface-mount components (like MLCC ceramic capacitors) to prevent structural stress micro-cracking during probing or mechanical handling.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">3. Metrology and Plating Inspection DFT Guidelines<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">To ensure non-destructive testing (NDT) compliance\u2014such as measuring through-hole barrel copper or surface finish thickness\u2014layout engineers must integrate metrology-specific guidelines:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502                   Metrology-Focused DFT Checklist                      \u2502\n\u251c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 \u2022 Thru-Hole Access: Reserve designated non-functional vias for ETP probes\u2502\n\u2502 \u2022 Surface Pad Flatness: Maintain unmasked, flat areas for SRP-4 testing\u2502\n\u2502 \u2022 Calibration Zones: Allocate clean reference regions for calibration  \u2502\n\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\n<\/code><\/pre>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Thru-Hole (PTH) Accessibility:<\/strong> For critical power and ground barrels that require non-destructive eddy current verification, ensure hole diameters and surrounding annular rings accommodate <strong>Hitachi ETP and TRP probes<\/strong> in compliance with <strong>ASTM E376<\/strong> standards.<\/li>\n\n\n\n<li><strong>Surface Plating Test Coupons \/ Pads:<\/strong> Allocate flat, unmasked copper test regions (\u2265 2\uff0a2 mm) on panel borders or board corners to support SRP-4<strong> probes<\/strong> in conducting accurate 4-pin Kelvin micro-resistance measurements.<\/li>\n\n\n\n<li><strong>Calibration Compatibility:<\/strong> Design layout margins to allow operators to place certified Hitachi calibration standard plates or reference foils directly onto calibration zones without dismantling the test fixture.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">4. Electrical Net and Signal Integrity Guidelines<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Adding test points impacts electrical characteristics, especially in high-frequency and power distribution networks.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Stubs and Parasitic Capacitance:<\/strong> Minimize the trace length connecting a primary signal net to its test pad to reduce parasitic capacitance and inductive stubs that degrade signal integrity.<\/li>\n\n\n\n<li><strong>High-Speed &amp; Differential Pairs:<\/strong> Never place physical test pads directly on high-speed differential pairs (e.g., USB, PCIe, HDMI) or high-frequency clock lines, as the added stub impedance causes severe signal reflection and eye-diagram degradation. Use boundary-scan (IEEE 1149.4) or indirect monitoring instead.<\/li>\n\n\n\n<li><strong>Power and Ground Net Sizing:<\/strong> Ensure heavy power rails incorporate multiple distributed test points or dedicated wide-bus access pads to verify current distribution and voltage drop under load.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">5. Design for Test Rules<\/h3>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><td><strong>Design Parameter<\/strong><\/td><td><strong>Recommended Specification<\/strong><\/td><td><strong>Engineering Impact<\/strong><\/td><\/tr><\/thead><tbody><tr><td><strong>Min. Test Pad Size<\/strong><\/td><td>\u22650.8 mm diameter<\/td><td>Ensures secure physical contact for ATG probes and ICT pins.<\/td><\/tr><tr><td><strong>Pad-to-Component Distance<\/strong><\/td><td>1:1 ratio relative to component height<\/td><td>Prevents probe arm collisions and mechanical interference.<\/td><\/tr><tr><td><strong>Board Edge Buffer<\/strong><\/td><td>\u22652.0 mm clearance<\/td><td>Protects pads from edge-clamping and panel handling damage.<\/td><\/tr><tr><td><strong>High-Speed Nets<\/strong><\/td><td>Prohibited from direct physical probing<\/td><td>Preserves impedance matching and prevents signal reflection.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<figure class=\"wp-block-image size-full\"><img fetchpriority=\"high\" decoding=\"async\" width=\"554\" height=\"554\" src=\"https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test.jpg\" alt=\"Design For Test\" class=\"wp-image-4106\" srcset=\"https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test.jpg 554w, https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test-300x300-1.jpg 300w, https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test-150x150.jpg 150w, https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test-12x12.jpg 12w, https:\/\/welleltron.com\/wp-content\/uploads\/2026\/10\/Design-for-Test-100x100.jpg 100w\" sizes=\"(max-width: 554px) 100vw, 554px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">5. Design for Test Best Practices <\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Executing a successful Design for Test strategy goes beyond basic schematic checks; it requires aligning layout practices with high-precision testing hardware:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Optimizing for Flying Probe Systems (ATG Probes):<\/strong> Ensure that test pads are evenly distributed across the board surface. This allows <strong><a href=\"https:\/\/welleltron.com\/test-equipment\/atg-test-probe\/atg-3a101804-flying-probe\/\">ATG flying probe<\/a> systems<\/strong> to navigate rapidly between test points without mechanical stress or tip wear.<\/li>\n\n\n\n<li><strong>Non-Destructive Copper Thickness Inspection:<\/strong> In alignment with ASTM E376 standards, design test-friendly access holes or open surface areas so that non-destructive eddy current sensors\u2014such as Hitachi ETP and TRP probes\u2014can accurately measure barrel and surface plating thickness.<\/li>\n\n\n\n<li><strong>Micro-Resistance Surface Verification:<\/strong> Integrate flat, unmasked copper test regions to support <strong><a href=\"https:\/\/welleltron.com\/test-equipment\/srp-4-probe\/hitachi-srp-4-probe\/\">SRP-4 probes<\/a><\/strong> in conducting accurate 4-pin Kelvin micro-resistance measurements.<\/li>\n\n\n\n<li><strong>Calibration Standard Integrity:<\/strong> Pair your Design for Test station with certified <strong><a href=\"https:\/\/welleltron.com\/test-equipment\/calibration-standard-plate\/hitachi-srp-4-calibration-standard\/\">Hitachi calibration standard plates<\/a><\/strong> and NIST-traceable reference foils to guarantee that measurement baselines remain drift-free.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>1.what is dft testing DFT (Design for Test or Design for Testing) is a proactive engineering methodology that integrates test-friendly features directly into the hardware architecture of a PCB during the initial schematic and layout phases. 2. Design for Testability Objectives Implementing a structured dft design for test framework serves several critical economic and technical&#8230;<\/p>","protected":false},"author":1,"featured_media":0,"parent":2541,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_kad_blocks_custom_css":"","_kad_blocks_head_custom_js":"","_kad_blocks_body_custom_js":"","_kad_blocks_footer_custom_js":"","_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"left","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[],"tags":[],"class_list":["post-4054","page","type-page","status-publish","hentry"],"taxonomy_info":[],"featured_image_src_large":false,"author_info":{"display_name":"lucaismilelove@gmail.com","author_link":"https:\/\/welleltron.com\/fr\/blog\/author\/luciasmilelovegmail-com\/"},"comment_info":0,"_hostinger_reach_plugin_has_subscription_block":false,"_hostinger_reach_plugin_is_elementor":false,"spectra_custom_meta":{"_uagb_previous_block_counts":["a:90:{s:21:\"uagb\/advanced-heading\";i:0;s:15:\"uagb\/blockquote\";i:0;s:12:\"uagb\/buttons\";i:0;s:18:\"uagb\/buttons-child\";i:0;s:19:\"uagb\/call-to-action\";i:0;s:15:\"uagb\/cf7-styler\";i:0;s:11:\"uagb\/column\";i:0;s:12:\"uagb\/columns\";i:0;s:14:\"uagb\/container\";i:0;s:21:\"uagb\/content-timeline\";i:0;s:27:\"uagb\/content-timeline-child\";i:0;s:14:\"uagb\/countdown\";i:0;s:12:\"uagb\/counter\";i:0;s:8:\"uagb\/faq\";i:0;s:14:\"uagb\/faq-child\";i:0;s:10:\"uagb\/forms\";i:0;s:17:\"uagb\/forms-accept\";i:0;s:19:\"uagb\/forms-checkbox\";i:0;s:15:\"uagb\/forms-date\";i:0;s:16:\"uagb\/forms-email\";i:0;s:17:\"uagb\/forms-hidden\";i:0;s:15:\"uagb\/forms-name\";i:0;s:16:\"uagb\/forms-phone\";i:0;s:16:\"uagb\/forms-radio\";i:0;s:17:\"uagb\/forms-select\";i:0;s:19:\"uagb\/forms-textarea\";i:0;s:17:\"uagb\/forms-toggle\";i:0;s:14:\"uagb\/forms-url\";i:0;s:14:\"uagb\/gf-styler\";i:0;s:15:\"uagb\/google-map\";i:0;s:11:\"uagb\/how-to\";i:0;s:16:\"uagb\/how-to-step\";i:0;s:9:\"uagb\/icon\";i:0;s:14:\"uagb\/icon-list\";i:0;s:20:\"uagb\/icon-list-child\";i:0;s:10:\"uagb\/image\";i:0;s:18:\"uagb\/image-gallery\";i:0;s:13:\"uagb\/info-box\";i:0;s:18:\"uagb\/inline-notice\";i:0;s:11:\"uagb\/lottie\";i:0;s:21:\"uagb\/marketing-button\";i:0;s:10:\"uagb\/modal\";i:0;s:18:\"uagb\/popup-builder\";i:0;s:16:\"uagb\/post-button\";i:0;s:18:\"uagb\/post-carousel\";i:0;s:17:\"uagb\/post-excerpt\";i:0;s:14:\"uagb\/post-grid\";i:0;s:15:\"uagb\/post-image\";i:0;s:17:\"uagb\/post-masonry\";i:0;s:14:\"uagb\/post-meta\";i:0;s:18:\"uagb\/post-taxonomy\";i:0;s:18:\"uagb\/post-timeline\";i:0;s:15:\"uagb\/post-title\";i:0;s:20:\"uagb\/restaurant-menu\";i:0;s:26:\"uagb\/restaurant-menu-child\";i:0;s:11:\"uagb\/review\";i:0;s:12:\"uagb\/section\";i:0;s:14:\"uagb\/separator\";i:0;s:11:\"uagb\/slider\";i:0;s:17:\"uagb\/slider-child\";i:0;s:17:\"uagb\/social-share\";i:0;s:23:\"uagb\/social-share-child\";i:0;s:16:\"uagb\/star-rating\";i:0;s:23:\"uagb\/sure-cart-checkout\";i:0;s:22:\"uagb\/sure-cart-product\";i:0;s:15:\"uagb\/sure-forms\";i:0;s:22:\"uagb\/table-of-contents\";i:0;s:9:\"uagb\/tabs\";i:0;s:15:\"uagb\/tabs-child\";i:0;s:18:\"uagb\/taxonomy-list\";i:0;s:9:\"uagb\/team\";i:0;s:16:\"uagb\/testimonial\";i:0;s:14:\"uagb\/wp-search\";i:0;s:19:\"uagb\/instagram-feed\";i:0;s:10:\"uagb\/login\";i:0;s:17:\"uagb\/loop-builder\";i:0;s:18:\"uagb\/loop-category\";i:0;s:20:\"uagb\/loop-pagination\";i:0;s:15:\"uagb\/loop-reset\";i:0;s:16:\"uagb\/loop-search\";i:0;s:14:\"uagb\/loop-sort\";i:0;s:17:\"uagb\/loop-wrapper\";i:0;s:13:\"uagb\/register\";i:0;s:19:\"uagb\/register-email\";i:0;s:24:\"uagb\/register-first-name\";i:0;s:23:\"uagb\/register-last-name\";i:0;s:22:\"uagb\/register-password\";i:0;s:30:\"uagb\/register-reenter-password\";i:0;s:19:\"uagb\/register-terms\";i:0;s:22:\"uagb\/register-username\";i:0;}"],"_edit_lock":["1792316221:1"],"rank_math_seo_score":["73"],"rank_math_internal_links_processed":["1"],"_edit_last":["1"],"rank_math_focus_keyword":["Design for Test"],"rank_math_title":["DFT: Design for Test"],"rank_math_og_content_image":["a:2:{s:5:\"check\";s:32:\"eef1bf62bd3b69a7b77933764fc7934b\";s:6:\"images\";a:1:{i:0;i:4106;}}"],"_wp_page_template":["default"],"_uag_custom_page_level_css":[""],"_kad_blocks_custom_css":[""],"_kad_blocks_head_custom_js":[""],"_kad_blocks_body_custom_js":[""],"_kad_blocks_footer_custom_js":[""],"_kad_post_transparent":[""],"_kad_post_title":[""],"_kad_post_layout":["left"],"_kad_post_sidebar_id":[""],"_kad_post_content_style":[""],"_kad_post_vertical_padding":[""],"_kad_post_feature":[""],"_kad_post_feature_position":[""],"_kad_post_header":[""],"_kad_post_footer":[""],"footnotes":[""],"_elementor_edit_mode":[""],"_elementor_template_type":[""],"_elementor_data":[""],"_elementor_conditions":["a:0:{}"],"_uag_css_file_name":["uag-css-4054.css"],"_elementor_page_assets":["a:0:{}"],"_uag_page_assets":["a:9:{s:3:\"css\";s:260:\".uag-blocks-common-selector{z-index:var(--z-index-desktop) !important}@media(max-width: 976px){.uag-blocks-common-selector{z-index:var(--z-index-tablet) !important}}@media(max-width: 767px){.uag-blocks-common-selector{z-index:var(--z-index-mobile) !important}}\";s:2:\"js\";s:0:\"\";s:18:\"current_block_list\";a:29:{i:0;s:23:\"kadence\/tableofcontents\";i:1;s:12:\"core\/heading\";i:2;s:23:\"kadence\/advancedheading\";i:3;s:14:\"core\/paragraph\";i:4;s:9:\"core\/list\";i:5;s:14:\"core\/list-item\";i:6;s:10:\"core\/table\";i:7;s:9:\"core\/code\";i:8;s:10:\"core\/image\";i:9;s:10:\"core\/group\";i:10;s:12:\"core\/columns\";i:11;s:14:\"core\/tag-cloud\";i:12;s:17:\"core\/social-links\";i:13;s:10:\"core\/video\";i:14;s:15:\"core\/media-text\";i:15;s:10:\"core\/audio\";i:16;s:10:\"core\/verse\";i:17;s:14:\"core\/pullquote\";i:18;s:17:\"core\/preformatted\";i:19;s:12:\"core\/details\";i:20;s:14:\"core\/page-list\";i:21;s:18:\"core\/legacy-widget\";i:23;s:16:\"core\/social-link\";i:24;s:12:\"kadence\/form\";i:25;s:14:\"kadence\/search\";i:26;s:16:\"kadence\/iconlist\";i:27;s:16:\"kadence\/listitem\";i:28;s:12:\"kadence\/icon\";i:29;s:19:\"kadence\/single-icon\";}s:8:\"uag_flag\";b:0;s:11:\"uag_version\";s:10:\"1793026345\";s:6:\"gfonts\";a:0:{}s:10:\"gfonts_url\";s:0:\"\";s:12:\"gfonts_files\";a:0:{}s:14:\"uag_faq_layout\";b:0;}"]},"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"trp-custom-language-flag":false,"woocommerce_thumbnail":false,"woocommerce_single":false,"woocommerce_gallery_thumbnail":false},"uagb_author_info":{"display_name":"lucaismilelove@gmail.com","author_link":"https:\/\/welleltron.com\/fr\/blog\/author\/luciasmilelovegmail-com\/"},"uagb_comment_info":0,"uagb_excerpt":"1.what is dft testing DFT (Design for Test or Design for Testing) is a proactive engineering methodology that integrates test-friendly features directly into the hardware architecture of a PCB during the initial schematic and layout phases. 2. Design for Testability Objectives Implementing a structured dft design for test framework serves several critical economic and technical...","_links":{"self":[{"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/pages\/4054","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/comments?post=4054"}],"version-history":[{"count":2,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/pages\/4054\/revisions"}],"predecessor-version":[{"id":4164,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/pages\/4054\/revisions\/4164"}],"up":[{"embeddable":true,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/pages\/2541"}],"wp:attachment":[{"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/media?parent=4054"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/categories?post=4054"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/welleltron.com\/fr\/wp-json\/wp\/v2\/tags?post=4054"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}